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SH7018 Datasheet(PDF) 164 Page - Renesas Technology Corp |
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SH7018 Datasheet(HTML) 164 Page - Renesas Technology Corp |
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164 / 431 page ![]() 148 Status Flag Clearing Timing: The status flag is cleared when the CPU reads a 1 status followed by a 0 write. Figure 8.38 shows the timing for status flag clearing by the CPU. Status flag Interrupt request signal Address Write signal φ T1 T2 TSR write cycle TSR address Figure 8.38 Timing of Status Flag Clearing by the CPU 8.7 Notes and Precautions This section describes contention and other matters requiring special attention during MTU operations. Note on Cycle Setting: When setting a counter clearing by compare-match, clearing is done in the final state when TCNT matches the TGR value (update timing for count value on TCNT match). The actual number of states set in the counter is given by the following equation: f = (N + 1) φ (f: counter frequency, φ: operating frequency, N: value set in the TGR) Contention between TCNT Write and Clear: If a counter clear signal is issued in the T 2 state during the TCNT write cycle, TCNT clearing has priority, and TCNT write is not conducted (figure 8.39). |
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