SH7018 datasheet(256/431 Pages) RENESAS

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In transmitting serial data, the SCI1 operates as follows:

1. The SCI1 monitors the TDRE bit in the SSR1. When TDRE is cleared to 0 the SCI1

recognizes that the transmit data register (TDR1) contains new data, and loads this data from

the TDR1 into the transmit shift register (TSR1).

2. After loading the data from the TDR1 into the TSR1, the SCI1 sets the TDRE bit to 1 and

starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCR1 is set to 1,

the SCI1 requests a transmit-data-empty interrupt (TxI) at this time.

Serial transmit data is transmitted in the following order from the TxD pin:

a. Start bit: one 0 bit is output.

b. Transmit data: seven or eight bits are output, LSB first.

c. Multiprocessor bit: one multiprocessor bit (MPBT value) is output.

d. Stop bit: one or two 1 bits (stop bits) are output.

e. Marking: output of 1 bits continues until the start bit of the next transmit data.

3. The SCI1 checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI1 loads data

from the TDR1 into the TSR1, outputs the stop bit, then begins serial transmission of the next

frame. If TDRE is 1, the SCI1 sets the TEND bit in the SSR1 to 1, outputs the stop bit, then

continues output of 1 bits in the marking state. If the transmit-end interrupt enable bit (TEIE)

in the SCR1 is set to 1, a transmit-end interrupt (TEI) is requested at this time.

Figure 12.11 shows an example of SCI1 receive operation in the multiprocessor format.

TDRE

TEND

TxI interrupt

handler writes

data in TDR1 and

clears TDRE to 0

TxI

interrupt

request

TEI

interrupt

request

1 frame

0/1

Multiprocessor

bit

Multiprocessor

bit

Serial

data

Start

bit

Data

Stop

bit

Start

bit

Data

Stop

bit

Idle

(marking

state)

0/1

TxI

interrupt

request

Figure 12.11 SCI1 Multiprocessor Transmit Operation (8-Bit Data with Multiprocessor Bit

and One Stop Bit)

SH7018 Datasheet(PDF) 256 Page - Renesas Technology Corp

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