SH7052 datasheet(341/919 Pages) RENESAS

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Offset Base Registers 1 and 2 (OSBR1, OSBR2)

Bit:

Initial value:

R/W:

OSBR1 and OSBR2 are 16-bit read-only registers used exclusively for input capture. OSBR1 and

OSBR2 use the channel 0 ICR0A input capture register input as their trigger signal, and store the

TCNT1A or TCNT2A value on detection of an edge.

The OSBR registers can only be accessed by a word read.

The OSBR registers are initialized to H'0000 by a power-on reset, and in hardware standby mode

and software standby mode.

For details, see sections 10.3.8, Twin-Capture Function.

10.2.22

Cycle Registers (CYLR)

The cycle registers (CYLR) are 16-bit registers. The ATU-II has eight cycle registers, four each in

channels 6 and 7.

Channel

Abbreviation

Function

CYLR6A to CYLR6D

16-bit PWM cycle registers

CYLR7A to CYLR7D

Cycle Registers (CYLR6A to CYLR6D, CYLR7A to CYLR7D)

Bit:

Initial value:

R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

The CYLR registers are 16-bit readable/writable registers used for PWM cycle storage.

The CYLR value is constantly compared with the corresponding free-running counter (TCNT6A

to TCNT6D, TCNT7A to TCNT7D) value, and when the two values match, the corresponding

timer start register (TSR) bit (CMF6A to CMF6D, CMF7A to CMF7D) is set to 1, and the free-

running counter (TCNT6A to TCNT6D, TCNT7A to TCNT7D) is cleared. At the same time, the

buffer register (BFR) value is transferred to the duty register (DTR).

SH7052 Datasheet(PDF) 341 Page - Renesas Technology Corp