SH7052 datasheet(338/919 Pages) RENESAS

338 / 919 page

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The ICR registers are initialized to H'00000000 by a power-on reset, and in hardware standby

mode and software standby mode.

10.2.20

General Registers (GR)

The general registers (GR) are 16-bit registers. The ATU-II has 36 general registers: eight each in

channels 1 and 2, four each in channels 3 to 5, six in channel 9, and two in channel 11.

Channel

Abbreviation

Function

GR1A to GR1H

Dual-purpose input capture and output compare registers

GR2A to GR2H

GR3A to GR3D

GR4A to GR4D

GR5A to GR5D

GR9A to GR9F

Dedicated output compare registers

GR11A, GR11B

Compare match registers

General Registers 1A to 1H and 2A to 2H (GR1A to GR1H, GR2A to GR2H)

Bit:

Initial value:

R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

These GR registers are 16-bit readable/writable registers with both input capture and output

compare functions. Function switching is performed by means of the timer I/O control registers

(TIOR).

When a general register is used for input capture, it stores the TCNT1A or TCNT2A value on

detection of an input capture signal from an external source. The corresponding IMF bit in TSR is

set to 1 at this time. The input capture signal edge to be detected is specified by the corresponding

TIOR.

When a general register is used for output compare, the GR value and free-running counter

(TCNT1A, TCNT2A) value are constantly compared, and when both values match, the IMF bit in

the timer status register (TSR) is set to 1. If connection of channels 1 and 2 and channel 8 is

specified in the timer connection register (TCNR), the corresponding channel 8 down-counter

(DCNT) is started. Compare-match output is specified by the corresponding TIOR.

The GR registers can only be accessed by a word read or write.

SH7052 Datasheet(PDF) 338 Page - Renesas Technology Corp