SH7052 datasheet(340/919 Pages) RENESAS

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In addition, channel 3 (GR3A to GR3D) input capture can be generated by GR9A to GR9D

compare-matches. This function is set by TRG3xEN in the timer control register (TCR).

The GR registers can be accessed by a byte read or write.

The GR registers are initialized to H'FF by a power-on reset, and in hardware standby mode and

software standby mode.

General Registers 11A, B (GR11A, B)

Bit:

Initial value:

R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

These GR registers are 16-bit readable/writable registers with compare-match function.

When a general register is used as a compare-match register, the GR value and free-running

counter (TCNT) value are constantly compared, and when both values match, the IMF bit in the

timer status register (TSR) is set to 1. Compare-match output is specified by the corresponding

TIOR.

GR11A and GR11B compare-mach signals are transmitted to the advanced pulse controller

(APC). For details, see section 11, Advanced Pulse Controller (APC).

The GR registers can only be accessed by a word read or write.

The GR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and

software standby mode.

10.2.21

Offset Base Registers (OSBR)

The offset base registers (OSBR) are 16-bit registers. The ATU-II has two OSBR registers, one

each in channels 1 and 2.

Channel

Abbreviation

Function

OSBR1

Dedicated input capture registers with signal from channel 0

OSBR2

ICR0A as input trigger

SH7052 Datasheet(PDF) 340 Page - Renesas Technology Corp