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SH7052 Datasheet(PDF) 354 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 354 Page - Renesas Technology Corp |
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354 / 919 page  328 • Bit 3—Reserved: This bit always reads 0. The write value should always be 0. • Bits 2 to 0—I/O Control 10G2 to 10G0 (IO10G2 to IO10G0): These bits select the function of general register 10G (GR10G). Bit 2: IO10G2 Bit 1: IO10G1 Bit 0: IO10G0 Description 0 0 0 GR is an output compare register Compare-match disabled (Initial value) 1 GR10G = TCNT10G compare-match 1 * Cannot be used 1 ** Cannot be used Timer Control Register 10 (TCR10): TCR10 is an 8-bit readable/writable register that selects the correction counter clear register (TCCLR10) compare-match counter clear source, enables or disables the noise canceler function, and selects the external input (TI10) edge. TCR10 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Bit: 7 6 5 43210 TRG2BEN TRG1BEN TRG2AEN TRG1AEN TRG0DEN NCE CKEG1 CKEG0 Initial value: 0 0 0 00000 R/W: R/W R/W R/W R/W R/W R/W R/W R/W • Bit 7—Trigger 2B Enable (TRG2BEN): Enables or disables counter clearing for channel 2 TCNT2B. If TCNT2B counts while clearing is enabled, TCNT2B will be cleared. Bit 7: TRG2BEN Description 0 Channel 2 counter B (TCNT2B) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value) 1 Channel 2 counter B (TCNT2B) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is enabled |
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