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SH7052 Datasheet(PDF) 355 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 355 Page - Renesas Technology Corp |
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355 / 919 page  329 • Bit 6—Trigger 1B Enable (TRG1BEN): Enables or disables counter clearing for channel 1 TCNT1B. If TCNT1B counts while clearing is enabled, TCNT1B will be cleared. Bit 6: TRG1BEN Description 0 Channel 1 counter B (TCNT1B) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value) 1 Channel 1 counter B (TCNT1B) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is enabled • Bit 5—Trigger 2A Enable (TRG2AEN): Enables or disables counter clearing for channel 2 TCNT2A. If TCNT2A counts while clearing is enabled, TCNT2A will be cleared. Bit 5: TRG2AEN Description 0 Channel 2 counter 2A (TCNT2A) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value) 1 Channel 2 counter 2A (TCNT2A) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is enabled • Bit 4—Trigger 1A Enable (TRG1AEN): Enables or disables counter clearing for channel 1 TCNT1A. If TCNT1A counts while clearing is enabled, TCNT1A will be cleared. Bit 4: TRG1AEN Description 0 Channel 1 counter 1A (TCNT1A) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value) 1 Channel 1 counter 1A (TCNT1A) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is enabled • Bit 3—Trigger 0D Enable (TRG0DEN): Enables or disables channel 0 ICR0D input capture signal requests. Bit 3: TRG0DEN Description 0 Capture requests for channel 0 input capture register (ICR0D) on event counter (TCNT10B) compare-match are disabled (Initial value) 1 Capture requests for channel 0 input capture register (ICR0D) on event counter (TCNT10B) compare-match are enabled |
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