SH7052 datasheet(359/919 Pages) RENESAS

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• Bit 1—Input Capture Interrupt Enable 10A (ICE10A): Enables or disables interrupt requests

by ICF10A in TSR10 when ICF10A is set to 1.

Bit 1: ICE10A

Description

ICI10A interrupt requested by ICF10A is disabled

(Initial value)

ICI10A interrupt requested by ICF10A is enabled

• Bit 0—Compare-Match Interrupt Enable 10A (CME10A): Enables or disables interrupt

requests by CMF10A in TSR10 when CMF10A is set to 1.

Bit 0: CME10A

Description

CMI10A interrupt requested by CMF10A is disabled

(Initial value)

CMI10A interrupt requested by CMF10A is enabled

10.3

Operation

10.3.1

Overview

The ATU-II has twelve timers of eight kinds in channels 0 to 11. It also has a built-in prescaler

that generates input clocks, and it is possible to generate or select internal clocks of the required

frequency independently of circuitry outside the ATU-II.

The operation of each channel and the prescaler is outlined below.

Channel 0: Channel 0 has a 32-bit free-running counter (TCNT0) and four 32-bit input capture

registers (ICR0A to ICR0D). TCNT0 is an up-counter that performs free-running operation. An

interrupt request can be generated on counter overflow. The four input capture registers (ICR0A to

ICR0D) capture the free-running counter (TCNT0) value by means of input from the

corresponding external signal input pin (TI0A to TI0D). For capture by means of input from an

external signal input pin, rising edge, falling edge, or both edges can be selected in the timer I/O

control register (TIOR0). In the case of input capture register 0D (ICR0D) only, capture can be

performed by means of a compare-match between free-running counter 10B (TCNT10B) and

compare-match register 10B (OCR10B), by making a setting in timer control register 10 (TCR10).

In this case, capture is performed even if an input capture disable setting has been made for

TIOR0. In each case, the DMAC can be activated or an interrupt requested when capture occurs.

Channel 0 also has three interval interrupt request registers (ITVRR1, ITVRR2A, ITVRR2B). A/D

converter (AD0 to AD2) activation can be selected by setting 1 in ITVA6 to ITVA13 in ITVRR,

and an interrupt request to the CPU by setting 1 in ITVE6 to ITVE13. These operations are

performed when the corresponding bit of bits 6 to 13 in TCNT0 changes to 1, enabling use as an

interval timer function.

SH7052 Datasheet(PDF) 359 Page - Renesas Technology Corp