SH7052 datasheet(363/919 Pages) RENESAS

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the corresponding external input pin. Incrementing on the rising edge, falling edge, or both edges

can be selected by means of settings in the timer control registers (TCR9A to TCR9C). An event

counter is cleared by edge input after a match with the corresponding general register. An interrupt

can requested when an event counter is cleared.

Timer control register (TCR9A, TCR9B) settings can be made to enable event counters ECNT9A

to ECNT9D to send a compare-match signal to channel 3 when the count matches the

corresponding general register (GR9A to GR9D), allowing input capture to be performed on

channel 3. This enables the pulse input interval to be measured.

Channel 10: Channel 10 generates a multiplied clock based on external input, and supplies this to

channels 1 to 5. Channel 10 is divided into three blocks: (1) an inter-edge measurement block, (2)

a multiplied clock generation block, and (3) a multiplied clock correction block.

(1) Inter-edge measurement block

This block has a 32-bit free-running counter (TCNT10A), 32-bit input capture register

(ICR10A), 32-bit output compare register (OCR10A), 8-bit event counter (TCNT10B), 8-bit

output compare register (OCR10B), 8-bit noise canceler counter (TCNT10H), and 8-bit noise

canceler compare-match register (NCR10).

The 32-bit free-running counter (TCNT10A) is an up-counter that performs free-running

operations. When input capture is performed by means of TI10 input, this counter is cleared to

H'00000001. When free-running counter (TCNT10A) reaches the value set in the output

compare register (OCR10A), a compare-match interrupt can be requested.

The input capture register (ICR10A) has an external signal input pin (TI10), and the free-

running counter (TCNT10A) value can be captured by means of input from TI10. Rising edge,

falling edge, or both edges can be selected by making a setting in bits CKEG1 and CKEG0 in

the timer control register (TCR10). The TI10 input has a noise canceler function, which can be

enabled by setting the NCE bit in the timer control register (TCR10). When the counter value

is captured, TCNT10A is cleared to 0 and an interrupt can be requested. The captured value

can be transferred to the multiplied clock generation block reload register (RLD10C).

The 8-bit event counter (TCNT10B) is an up-counter that is incremented by TI10 input. When

the event counter (TCNT10B) value reaches the value set in the output compare register

(OCR10B), a compare-match interrupt can be requested. By setting the TRG0DEN bit in the

timer control register (TCR10), a capture request can also be issued for the channel 0 input

capture register 0D (ICR0D) when compare-match occurs.

The 8-bit noise canceler counter (TCNT10H) and 8-bit noise canceler compare-match register

(NCR10) are used to set the period for which the noise canceler functions. By setting a value in

the noise canceler compare-match register (TCNT10H) and setting the NCE bit in the timer

control register (TCR10), TI10 input is masked when it occurs. At the same time as TI10 input

is masked, the noise canceler counter (TCNT10H) starts counting up on the P

φx10 clock.

SH7052 Datasheet(PDF) 363 Page - Renesas Technology Corp