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SH7052 Datasheet(PDF) 367 Page - Renesas Technology Corp

Part # SH7052
Description  SuperHTM RISC engine
PDF  919 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7052 Datasheet(HTML) 367 Page - Renesas Technology Corp

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341
Pø
TCNT3
Clock
TCNT3
GR3D
(period)
TSR3
IMF3D
Cleared by software
Cleared by software
0005
0004
0003
0002
0001
0000
0008
0007
0003
0002
0008
0008
0001
0000
0008
Figure 10.14 Example of Cyclic Counter Operation
10.3.3
Compare-Match Function
Designating general registers in channels 1 to 5 (GR1A to GR1H, GR2A to GR2H, GR3A to
GR3D, GR4A to GR4D, GR5A to GR5D) for compare-match operation in the timer I/O control
registers (TIOR1 to TIOR5) enables compare-match output to be performed at the corresponding
external pins (TIO1A to TIO1H, TIO2A to TIO2H, TIO3A to TIO3D, TIO4A to TIO4D, TIO5A
to TIO5D).
A free-running counter (TCNT) starts counting up when 1 is set in the timer status register
(TSTR). When the desired number is set beforehand in GR, and the TCNT value matches the GR
value, the timer status register (TSR) bit corresponding to GR is set and a waveform is output from
the corresponding external pin.
1 output, 0 output, or toggle output can be selected by means of a setting in TIOR. If the
appropriate interrupt enable register (TIER) setting is made, an interrupt request will be sent to the
CPU when a compare-match occurs.
Channel 1 and 2 compare-match registers (OCR1, OCR2A to OCR2H) perform compare-match
operations unconditionally. However, there are no corresponding output pins. If the appropriate
TIER setting is made, an interrupt request will be sent to the CPU when a compare-match occurs.
Channel 1 and 2 GR and OCR registers can send a trigger/terminate signal to channel 8 when a
compare-match occurs. In this case, settings should be made in the trigger mode register
(TRGMDR), timer connection register (TCNR), and one-shot pulse terminate register (OTR).
An example of compare-match operation is shown in figure 10.15.
In the example in figure 10.15, channel 1 is activated, and external output is performed with toggle
output specified for GR1A, 1 output for GR1B, and 0 output for GR1C.



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