SH7052 datasheet(366/919 Pages) RENESAS

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corresponding timer interrupt enable register (TIER) is set to 1 at this time, an interrupt request is

sent to the CPU. After overflowing, TCNT starts counting up again from H'00000000 or H'0000.

If the TSTR value is cleared to 0 during TCNT operation, the corresponding TCNT halts. In this

case, TCNT is not reset. If external output is being performed from the GR for the corresponding

TCNT, the output value does not change.

Channel 0 free-running counter operation is shown in figure 10.13.

FFFFFFFD

Pø

TSTR

TST0

TCNT0

Clock

TCNT0

TSR0

OVF0

Cleared by software

00000002

00000001

00000000

FFFFFFFF

FFFFFFFE

00000005

00000004

00000003

00000002

00000001

Figure 10.13 Free-Running Counter Operation and Overflow Timing

The free-running counters (TCNT) in ATU-II channels 6 and 7 perform cyclic count operations

unconditionally. With channel 3 to 5 free-running counters (TCNT), when the corresponding

T3PWM to T5PWM bit in the timer mode register (TMDR) is set to 1, or the corresponding CCI

bit in the timer I/O control register (TIOR) is set to 1 when bits T3PWM to T5PWM are 0, the

counter for the relevant channel performs a cyclic count. The relevant TCNT counter is cleared by

a compare-match of TCNT with GR3D, GR4D, or GR5D in channel 3 to 5, or CYLR in channels

6 and 7 (counter clear function). TCNT starts counting up as a cyclic counter when the

corresponding STR bit in TSTR is set to 1 after the TMDR setting is made. When the count value

matches the GR3D, GR4D, GR5D, or CYLR value, the corresponding IMF3D, IMF4D, or IMF5D

bit in the timer status register (TSR) (or the CMF bit in TSR6 or TSR7 for channels 6 and 7) is set

to 1, and TCNT is cleared to H'0000 (H'0001 in channels 6 and 7).

If the corresponding TIER bit is set to 1 at this time, an interrupt request is sent to the CPU. After

the compare-match, TCNT starts counting up again from H'0000 (H'0001 in channels 6 and 7).

Figure 10.14 shows the operation when channel 3 is used as a cyclic counter (with a cycle setting

of H'0008).

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