SH7052 datasheet(362/919 Pages) RENESAS

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Channels 6 and 7: Channels 6 and 7 each have 16-bit free-running counters (TCNT6A to

TCNT6D, TCNT7A to TCNT7D), 16-bit cycle registers (CYLR6A to CYLR6D, CYLR7A to

CYLR7D), 16-bit duty registers (DTR6A to DTR6D, DTR7A to DTR7D), and buffer registers

(BFR6A to BFR6D, BFR7A to BFR7D). Channels 6 and 7 also each have external output pins

(TO6A to TO6D, TO7A to TO7D), and can be used as buffered PWM timers. The TCNT registers

are up-counters, and 0 is output to the corresponding external output pin when the TCNT value

matches the DTR value (when DTR

≠ CYLR). When the TCNT value matches the CYLR value

(when DTR

≠ H'0000), 1 is output to the external output pin, TCNT is initialized to H'0001, and

the BFR value is transferred to DTR. Thus, the configuration of channels 6 and 7 enables them to

perform waveform output with the CYLR value as the cycle and the DTR value as the duty, and to

use BFR to absorb the time lag between setting of data in DTR and compare-match occurrence.

When DTR = CYLR, 1 is output continuously to the external output pin, giving a duty of 100%.

When DTR = H'0000, 0 is output continuously to the external output pin, giving a duty of 0%. Do

not set a value in DTR that will result in the condition DTR > CYLR.

In channel 6, TCNT can also be designated for complementary PWM output by means of the

PWM mode register (PMDR). When the corresponding TSTR is set to 1, TCNT starts counting

up, then switches to a down-count when the count matches the CYLR value. When TCNT reaches

H'0000, it starts counting up again. When TCNT = DTR, the corresponding TO6A to TO6D

output changes. Whether TCNT is counting up or down can be ascertained from the timer status

DMAC activation and interrupt request generation, respectively, are possible when TCNT =

CYLR in asynchronous PWM mode, and when TCNT = H'0000 in complementary PWM mode.

Channel 8: Channel 8 has sixteen 16-bit down-counters (DCNT8A to DCNT8P). The down-

counters have corresponding external signal output pins, and can generate one-shot pulses. Setting

a value in DCNT and setting the corresponding bit to 1 in the down-count start register (DSTR)

starts DCNT operation and simultaneously outputs 1 to the external output pin. When DCNT

counts down to H'0000, it stops and outputs 0 to the external output pin. An interrupt can be

requested when DCNT underflows.

Down-counter operation can be coupled with the channel 1 or channel 2 output compare function

by means of settings in the timer connection register (TCNR) and one-shot pulse terminate register

(OTR), respectively, so that DCNT8I to DCNT8H count operations are started and stopped from

channel 1, and DCNT8I to DCNT8P count operations from channel 2.

DCNT8I to DCNT8P have a reload register (RLDR), and a setting in the reload enable register

(RLDEN) enables count operations to be started after reading the value from this register.

Channel 9: Channel 9 has six 8-bit event counters (ECNT9A to ECNT9F) and six 8-bit general

registers (GR9A to GR9F). The event counters are up-counters, each with a corresponding

external input pin (ECNT9A to ECNT9F). The event counter value is incremented by input from

SH7052 Datasheet(PDF) 362 Page - Renesas Technology Corp