SH7052 datasheet(361/919 Pages) RENESAS

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TIOR2D). When used as output compare registers, a compare-match can be used as a one-shot

pulse terminate trigger by setting the channel 8 one-shot pulse terminate register (OTR), and using

this in combination with the down-counters (DCNT8A to DCNT8H).

In the case of the output compare registers (OCR2A to OCR2H), a TCNT2B compare-match can

be used as a one-shot pulse start trigger by setting the channel 8 timer connection register (TCNR),

and using this in combination with the down-counters (DCNT8I to DCNT8P). An interrupt can be

requested on the occurrence of the respective input capture or compare-match.

In addition, channel 2 has a 16-bit dedicated input capture register (OSBR2). The channel 0 TI0A

input pin can also be used as the OSBR2 trigger input, enabling use of a twin-capture function.

Channels 3 to 5: Channels 3 to 5 each have a 16-bit free-running counter (TCNT3 to TCNT5) and

four 16-bit general registers (GR3A to GR3D, GR4A to GR4D, GR5A to GR5D). TCNT3 to

TCNT5 are up-counters that perform free-running operation. Channels 3 to 5 each have a 16-bit

free-running counter (TCNT3 to TCNT5) and four 16-bit general registers (GR3A to GR3D,

GR4A to GR4D, GR5A to GR5D). TCNT3 to TCNT5 are up-counters that perform free-running

operation. In addition, counter clearing can be performed by compare-match by making a setting

in the timer I/O control register (TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B). Each

counter can generate an interrupt request when it overflows.

The four general registers (GR3A to GR3D, GR4A to GR4D, GR5A to GR5D) each have

corresponding external signal I/O pins (TIO3A to TIO3D, TIO4A to TIO4D, TIO5A to TIO5D),

and can be used as input capture or output compare registers. When used for input capture, the

free-running counter (TCNT3 to TCNT5) value is captured by means of input from the

corresponding external signal I/O pin (TIO3A to TIO3D, TIO4A to TIO4D, TIO5A to TIO5D).

Rising edge, falling edge, or both edges can be selected for the input capture signal in the timer

I/O control registers (TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B). Also, in use for

input capture, input capture can be performed using a compare-match between a channel 9 event

counter (ECNT9A to ECNT9D), described later, and a general register (GR9A to GR9D) as the

trigger. In this case, capture is performed even if an input capture disable setting has been made

for TIOR3A to TIOR3D. When used for output compare, compare-match with the free-running

counter (TCNT3 to TCNT5) is performed. For the output from the external signal I/O pins by

compare-match, 0 output, 1 output, or toggle output can be selected in the timer I/O control

registers (TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B). An interrupt can be

requested on the occurrence of the respective input capture or compare-match. However, in the

case of input capture using channel 9 as a trigger, an interrupt request from channel 3 cannot be

used.

By selecting PWM mode in the timer mode register (TMDR), PWM output can be obtained, with

three outputs for each. In this case, GR3D, GR4D, and GR5D are automatically used as cycle

registers, and GR3A to GR3C, GR4A to GR4C, GR5A to GR5C, as duty registers. TCNT3 to

TCNT5 are cleared by the corresponding GR3D, GR4D, or GR5D compare-match.

SH7052 Datasheet(PDF) 361 Page - Renesas Technology Corp