SH7052 datasheet(358/919 Pages) RENESAS

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Timer Interrupt Enable Register 10 (TIER10): TIER10 is a 16-bit readable/writable register

that controls enabling/disabling of channel 10 input capture and compare-match interrupt requests.

TIER10 is initialized to H'0000 by a power-on reset, and in hardware standby mode and software

standby mode.

Bit:

——

———

—

Initial value:

R/W:

Bit:

——

—

IREG

CME10G CME10B ICE10A CME10A

Initial value:

R/W:

R/W

• Bits 15 to 5—Reserved: These bits always read 0. The write value should always be 0.

• Bit 4—Interrupt Enable Edge G (IREG): Specifies TSR10 CMF10G interrupt request timing.

Bit 4: IREG

Description

Interrupt is requested when CMF10G becomes 1

(Initial value)

Interrupt is requested by next external input (TI10) (AGCK) after CMF10G

becomes 1

• Bit 3—Compare-Match Interrupt Enable 10G (CME10G): Enables or disables interrupt

requests by CMF10G in TSR10 when CMF10G is set to 1.

Bit 3: CME10G

Description

CMI10G interrupt requested by CMF10G is disabled

(Initial value)

CMI10G interrupt requested by CMF10G is enabled

• Bit 2—Compare-Match Interrupt Enable 10B (CME10B): Enables or disables interrupt

requests by CMF10B in TSR10 when CMF10B is set to 1.

Bit 2: CME10B

Description

CMI10B interrupt requested by CMF10B is disabled

(Initial value)

CMI10B interrupt requested by CMF10B is enabled

SH7052 Datasheet(PDF) 358 Page - Renesas Technology Corp