SH7052 datasheet(368/919 Pages) RENESAS

368 / 919 page

342

Pø

TCNT1

Clock

TCNT1

GR1A–1C

TIO1A

TIO1B

TIO1C

TSR1

IMF1A–1D

Channel 8

start/terminate

trigger signal

Cleared by software

0085

0084

0083

0082

0081

0080

007F

007E

003E

0040

003F

003E

003D

003C

Figure 10.15 Compare-Match Operation

10.3.4

Input Capture Function

If input capture registers (ICR0A to ICR0D) and general registers (GR1A to GR1H, GR2A to

GR2H, GR3A to GR3D, GR4A to GR4D, GR5A to GR5D) in channels 0 to 5 and 11 are

designated for input capture operation in the timer I/O control registers (TIOR0 to TIOR5), input

capture is performed when an edge is input at the corresponding external pins (TI0A to TI0D,

TIO1A to TIO1H, TIO2A to TIO2H, TIO3A to TIO3D, TIO4A to TIO4D, TIO5A to TIO5D).

A free-running counter (TCNT) starts counting up when a setting is made in the timer start register

(TSTR). When an edge is input at an external pin corresponding to ICR or GR, the corresponding

timer status register (TSR) bit is set and the TCNT value is transferred to ICR or GR. Rising-edge,

falling-edge, or both-edge detection can be selected. By making the appropriate setting in the

interrupt enable register (TIER), an interrupt request can be sent to the CPU.

SH7052 Datasheet(PDF) 368 Page - Renesas Technology Corp

SH7052 Datasheet(HTML) 368 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL