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SH7052 Datasheet(PDF) 524 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 524 Page - Renesas Technology Corp |
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524 / 919 page  498 0 123 4 5 6 7 123 4 5 123 4 5 67 8 9 10 11 12 13 14 15 9 10 11 12 13 14 15 08 0 Base clock Receive data (RxD) Synchronization sampling timing Data sampling timing 8 clocks 16 clocks Start bit –7.5 clocks +7.5 clocks D0 D1 Figure 14.25 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as: M = 0.5 – 1 2N D – 0.5 N – (L – 0.5) F – (1 + F) × 100% M : Receive margin (%) N : Ratio of clock frequency to bit rate (N = 16) D : Clock duty cycle (D = 0 to 1.0) L : Frame length (L = 9 to 12) F : Absolute deviation of clock frequency From the equation above, if F = 0 and D = 0.5 the receive margin is 46.875%: D = 0.5, F = 0 M = (0.5 – 1/(2 × 16)) × 100% = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20 to 30%. |
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