SH7052 datasheet(532/919 Pages) RENESAS

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15.2

15.2.1

Master Control Register (MCR)

The master control register (MCR) is an 8-bit readable/writable register that controls the CAN

interface.

Bit:

MCR7

—

MCR5

—

MCR2

MCR1

MCR0

Initial value:

R/W:

R/W

—

R/W

—

R/W

• Bit 7—HCAN Sleep Mode Release (MCR7): Enables or disables HCAN sleep mode release

by bus operation.

Bit 7: MCR7

Description

HCAN sleep mode release by CAN bus operation disabled

(Initial value)

HCAN sleep mode release by CAN bus operation enabled

• Bit 6—Reserved: This bit always reads 0. The write value should always be 0.

• Bit 5—HCAN Sleep Mode (MCR5): Enables or disables HCAN sleep mode transition.

Bit 5: MCR5

Description

HCAN sleep mode released

(Initial value)

Transition to HCAN sleep mode enabled

• Bits 4 and 3—Reserved: These bits always read 0. The write value should always be 0.

• Bit 2—Message Transmission Method (MCR2): Selects the transmission method for transmit

messages.

Bit 2: MCR2

Description

Transmission order determined by message identifier priority

(Initial value)

Transmission order determined by mailbox (buffer) number priority

(TXPR1 > TXPR15)

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