SH7052 datasheet(539/919 Pages) RENESAS

539 / 919 page

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• Bits 15 to 9 and 7 to 0—Transmit Wait Register (TXPR7 to 1, TXPR15 to 8): These bits set a

CAN bus arbitration wait for the corresponding mailboxes (buffers).

Bit x: TXPRx

Description

Transmit message idle state in corresponding mailbox

(Initial value)

[Clearing condition]

Message transmission completion and cancellation completion

Transmit message transmit wait in corresponding mailbox (CAN bus

arbitration)

• Bit 8—Reserved: This bit always reads 0. The write value should always be 0.

15.2.6

Transmit Wait Cancel Register (TXCR)

The transmit wait cancel register (TXCR) is a 16-bit readable/writable register that controls

cancellation of transmit wait messages in mailboxes (buffers).

Bit:

TXCR7

TXCR6

TXCR5

TXCR4

TXCR3

TXCR2

TXCR1

—

Initial value:

R/W:

R/W

Bit:

TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10

TXCR9

TXCR8

Initial value:

R/W:

R/W

• Bits 15 to 9 and 7 to 0—Transmit Wait Cancel Register (TXCR7 to 1, TXCR15 to 8): These

bits control cancellation of transmit wait messages in the corresponding HCAN mailboxes

(buffers).

Bit x: TXCRx

Description

Transmit message cancellation idle state in corresponding mailbox

(Initial value)

[Clearing condition]

Completion of TXPR clearing (when transmit message is canceled normally)

TXPR cleared for corresponding mailbox (transmit message cancellation)

• Bit 8—Reserved: This bit always reads 0. The write value should always be 0.

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