SH7052 datasheet(551/919 Pages) RENESAS

551 / 919 page

525

15.2.15

Transmit Error Counter (TEC)

The transmit error counter (TEC) is an 8-bit read-only register that functions as a counter

indicating the number of transmit message errors on the CAN bus. The count value is stipulated in

the CAN protocol.

Bit:

Initial value:

R/W:

15.2.16

Unread Message Status Register (UMSR)

The unread message status register (UMSR) is a 16-bit readable/writable register containing status

flags that indicate, for individual mailboxes (buffers), that a received message has been

overwritten by a new receive message before being read. When an unread message is overwritten

by a new receive message, the old data is lost.

Bit:

UMSR7

UMSR6

UMSR5

UMSR4

UMSR3

UMSR2

UMSR1

UMSR0

Initial value:

R/W:

R/W

Bit:

UMSR15

UMSR14 UMSR13

UMSR12 UMSR11

UMSR10

UMSR9

UMSR8

Initial value:

R/W:

R/W

• Bits 15 to 0—Unread Message Status Flags (UMSR7 to 0, UMSR15 to 8): Status flags

indicating that an unread receive message has been overwritten.

Bit x: UMSRx

Description

[Clearing condition]

Writing 1

(Initial value)

Unread receive message is overwritten by a new message

[Setting condition]

When a new message is received before RXPR is cleared

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