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SH7052 Datasheet(PDF) 548 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 548 Page - Renesas Technology Corp |
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548 / 919 page  522 15.2.13 Interrupt Mask Register (IMR) The interrupt mask register (IMR) is a 16-bit readable/writable register containing flags that enable or disable requests by individual interrupt sources. Bit: 15 14 13 12 11 10 9 8 IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 — Initial value: 1 1 1 1 1 1 1 0 R/W: R/W R/W R/W R/W R/W R/W R/W — Bit: 7 6 5 4 3 2 1 0 —— — IMR12 —— IMR9 IMR8 Initial value: 1 1 1 1 1 1 1 1 R/W: R R R R/W R R R/W R/W • Bit 15—Overload Frame/Bus Off Recovery Interrupt Mask (IMR7): Enables or disables overload frame/bus off recovery interrupt requests. Bit 15: IMR7 Description 0 Overload frame/bus off recovery interrupt request (OVR) by IRR7 to CPU enabled 1 Overload frame/bus off recovery interrupt request (OVR) by IRR7 to CPU disabled (Initial value) • Bit 14—Bus Off Interrupt Mask (IMR6): Enables or disables bus off interrupt requests caused by the transmit error counter. Bit 14: IMR6 Description 0 Bus off interrupt request (ERS) by IRR6 to CPU enabled 1 Bus off interrupt request (ERS) by IRR6 to CPU disabled (Initial value) • Bit 13—Error Passive Interrupt Mask (IMR5): Enables or disables error passive interrupt requests caused by the transmit/receive error counter. Bit 13: IMR5 Description 0 Error passive interrupt request (ERS) by IRR5 to CPU enabled 1 Error passive interrupt request (ERS) by IRR5 to CPU disabled (Initial value) |
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