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SH7052 Datasheet(PDF) 550 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 550 Page - Renesas Technology Corp |
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550 / 919 page ![]() 524 • Bit 4—Bus Operation Interrupt Mask (IMR12): Enables or disables interrupt requests due to bus operation in sleep mode. Bit 4: IMR12 Description 0 Bus operation interrupt request (OVR) by IRR12 to CPU enabled 1 Bus operation interrupt request (OVR) by IRR12 to CPU disabled (Initial value) • Bit 1—Unread Interrupt Mask (IMR9): Enables or disables unread receive message overwrite interrupt requests. Bit 1: IMR9 Description 0 Unread message overwrite interrupt request (OVR) by IRR9 to CPU enabled 1 Unread message overwrite interrupt request (OVR) by IRR9 to CPU disabled (Initial value) • Bit 0—Mailbox Empty Interrupt Mask (IMR8): Enables or disables mailbox empty interrupt requests. Bit 0: IMR8 Description 0 Mailbox empty interrupt request (SLE) by IRR8 to CPU enabled 1 Mailbox empty interrupt request (SLE) by IRR8 to CPU disabled (Initial value) 15.2.14 Receive Error Counter (REC) The receive error counter (REC) is an 8-bit read-only register that functions as a counter indicating the number of receive message errors on the CAN bus. The count value is stipulated in the CAN protocol. Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R |
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