Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

SH7052 Datasheet(PDF) 547 Page - Renesas Technology Corp

Part # SH7052
Description  SuperHTM RISC engine
PDF  919 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7052 Datasheet(HTML) 547 Page - Renesas Technology Corp

Back Button SH7052 Datasheet HTML 543Page - Renesas Technology Corp SH7052 Datasheet HTML 544Page - Renesas Technology Corp SH7052 Datasheet HTML 545Page - Renesas Technology Corp SH7052 Datasheet HTML 546Page - Renesas Technology Corp SH7052 Datasheet HTML 547Page - Renesas Technology Corp SH7052 Datasheet HTML 548Page - Renesas Technology Corp SH7052 Datasheet HTML 549Page - Renesas Technology Corp SH7052 Datasheet HTML 550Page - Renesas Technology Corp SH7052 Datasheet HTML 551Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 547 / 919 page
background image
521
• Bit 0—Mailbox Empty Interrupt Flag (IRR8): Status flag indicating that the next transmit
message can be stored in the mailbox.
Bit 0: IRR8
Description
0
[Clearing condition]
Writing 1
(Initial value)
1
Transmit message has been transmitted or aborted, and new message can
be stored
[Setting condition]
When TXPR (transmit wait register) is cleared by completion of transmission
or completion of transmission abort
15.2.12
Mailbox Interrupt Mask Register (MBIMR)
The mailbox interrupt mask register (MBIMR) is a 16-bit readable/writable register containing
flags that enable or disable individual mailbox (buffer) interrupt requests.
Bit:
15
14
13
12
11
10
9
8
MBIMR7
MBIMR6
MBIMR5
MBIMR4
MBIMR3
MBIMR2
MBIMR1
MBIMR0
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9
MBIMR8
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Bits 15 to 0—Mailbox Interrupt Mask (MBIMR7 to 0, MBIMR15 to 8): Flags that enable or
disable individual mailbox interrupt requests.
Bit x: MBIMRx
Description
0
[Transmitting]
Interrupt request to CPU due to TXPR clearing
[Receiving]
Interrupt request to CPU due to RXPR setting
1
Interrupt requests to CPU disabled
(Initial value)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com