SH7052 datasheet(563/919 Pages) RENESAS

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Table 15.4

BCR Setting Limits

Name

Abbreviation

Min. Value

Max. Value

Unit

Time segment 1

TSEG1

Time segment 2

TSEG2

Baud rate prescaler

BRP

128

System

clock

Sample point

SAM

Point

Re-synchronization jump width

SJW

Settable Variable Limits

• The bit width consists of the total of the settable time quanta (TQ). TQ (number of system

clocks) is determined by the baud rate prescaler (BRP).

TQ = (2*(BRP + 1))/(f

CLK)

CLK = Pφ

• The minimum value of SJW is stipulated in the CAN specifications.

≥ SJW ≥ 1

• The minimum value of TSEG1 is stipulated in the CAN specifications.

TSEG1

≥ TSEG2

• The minimum value of TSEG2 is stipulated in the CAN specifications.

TSEG2

≥ (1 + SJW)

The following formula is used to calculate the baud rate.

fCLK

× (BRP + 1) × (3 + TSEG1 + TSEG2)

Bit rate [b/s] =

Note:

CLK = Pφ (peripheral clock: φ/2]

The BCR values are used for BRP, TSEG1, and TSEG2.

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