SH7052 datasheet(861/919 Pages) RENESAS

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24.3.8

Serial Communication Interface Timing

Table 24.13 shows serial communication interface timing.

Table 24.13 Serial Communication Interface Timing

Conditions: V

CC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V,

CC2 = 5.0 V ±0.5 V, AVCC = 5.0 V ±0.5 V, AVref = 4.5 V to AVCC,

SS = PLLVSS = AVSS = 0 V, Ta = –40°C to 85°C.

When PV

CC1 = 3.3 V ±0.3 V, VCC = PVCC1.

When writing or erasing flash EEPROM, T

a = –40°C to 85°C.

Item

Symbol

Min

Max

Unit

Figures

Clock cycle

scyc

—

cyc

Figure 24.15

Clock cycle (clock sync)

scyc

—

cyc

Clock pulse width

sckw

0.4

0.6

scyc

Input clock rise time

sckr

—

3.0

cyc

Input clock fall time

sckf

—

3.0

cyc

Transmit data delay time

TxD

—

100

Figure 24.16

Receive data setup time

RxS

100

—

Receive data hold time

RxH

100

—

[Operating precautions]

The inputs and outputs are asynchronous in start-stop synchronous mode, but as shown in figure

24.16, the receive data are judged to have been changed at CK clock rise (two-clock intervals).

The transmit signals change with a reference of CK clock rise (two-clock intervals).

tsckw

VIH

VIL

SCK0 to SCK2

tsckr

tsckf

tscyc

Figure 24.15 SCI Input/Output Timing

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