SH7052 datasheet(202/919 Pages) RENESAS

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Table 10.1 lists the functions of the ATU-II.

Table 10.1

ATU-II Functions

Item

Channel 0

Channel 1

Channel 2

Channels 3 to 5

Counter

configu-

ration

Clock

sources

φ to φ/32

(

φ to φ/32) × (1/2n)

(n = 0 to 5)

TCLKA, TCLKB

(

φ to φ/32) × (1/2n)

(n = 0 to 5)

TCLKA, TCLKB

(

φ to φ/32) × (1/2n)

(n = 0 to 5)

TCLKA, TCLKB

Counters

TCNT0H, TCNT0L

TCNT1A, TCNT1B

TCNT2A, TCNT2B

TCNT3 to 5

General

registers

—

GR1A to H

GR2A to H

GR3A to D,

GR4A to D,

GR5A to D

Dedicated

input

capture

ICR0AH, ICR0AL,

ICR0BH, ICR0BL,

ICR0CH, ICR0CL,

ICR0DH, ICR0DL

OSBR1

OSBR2

—

Dedicated

output

compare

—

OCR1

OCR2A to 2H

—

PWM

output

—

Duty: GR3A to C,

GR4A to C,

GR5A to C

Cycle: GR3D, GR4D,

GR5D

Input pins

TI0A to D

—

I/O pins

—

TIO1A to H

TIO2A to H

TIO3A to D,

TIO4A to D,

TIO5A to D

Output pins

————

Counter clearing

function

———O

Interrupt sources

6 sources

Interval

× 1,

input capture

× 4,

overflow

× 1

9 sources

Dual input capture/

compare-match

× 8,

overflow

× 1

9 sources

Dual input capture/

compare-match

× 8,

overflow

× 1*

(* Same vector)

15 sources

Dual input capture/

compare-match

× 12,

overflow

× 3

Inter-channel and

inter-module

connection signals

A/D converter

activation by interval

interrupt request,

DMAC activation by

input capture

interrupt, channel 10

compare-match

signal capture trigger

input

Compare-match

signal trigger output

to channel 8

one-shot pulse

output down-counter

Channel 10 compare-

match signal counter

clear input

Compare-match

signal trigger output

to channel 8

one-shot pulse

output down-counter

Channel 10 compare-

match signal counter

clear input

Channel 9 compare-

match signal input to

capture trigger

(Channel 3 only)

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