SH7052 datasheet(201/919 Pages) RENESAS

201 / 919 page

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• Channel 10 has a 32-bit output compare and input capture register, free-running counter, 16-bit

free-running counter, output compare/input capture register, reload register, 8-bit event

counter, and output compare register, and four 16-bit reload counters, allowing the following

operations:

 Capture on external input pin edge input

 Reload count possible with 32, 64, 128, or 256 times the captured value

 Internal clock generated by reload counter underflow can be used as 16-bit free-running

counter input

 Channel 1 and 2 free-running counter clearing capability

• Channel 11 has one 16-bit free-running counter and two 16-bit general registers, allowing the

following operations:

 Two general registers can be used for compare-match

 Compare-match signal can be output to APC

• High-speed access to internal 16-bit bus

 High-speed access to 16-bit bus for 16-bit registers: timer counters, compare registers, and

capture registers

• 75 interrupt sources

 Four input capture interrupt requests, one overflow interrupt request, and one interval

interrupt request for channel 0

 Sixteen dual input capture/compare-match interrupt requests and two counter overflow

interrupt requests for channels 1 and 2

 Twelve dual input capture/compare-match interrupt requests and three overflow interrupt

requests for channels 3 to 5

 Eight compare-match interrupts for channels 6 and 7

 Sixteen one-shot end interrupt requests for channel 8

 Six compare-match interrupts for channel 9

 Two compare-match interrupts and one dual-function input capture/compare-match

interrupt for channel 10

 Two dual input capture/compare-match interrupt requests and one overflow interrupt

request for channel 11

• Direct memory access controller (DMAC) activation

 The DMAC can be activated by a channel 0 input capture interrupt (ICI0A to D)

 The DMAC can be activated by a channel 6 cycle register 6 compare-match interrupt

(CMI6A to D)

 The DMAC can be activated by a channel 7 cycle register 7 compare-match interrupt

(CMI7A to D)

• A/D converter activation

 The A/D converter can be activated by detection of 1 in bits ITVA6 to 13 of the channel 0

interval interrupt request registers (ITVRR1, ITVRR2A, ITVRR2B)

SH7052 Datasheet(PDF) 201 Page - Renesas Technology Corp