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SH7052 Datasheet(PDF) 218 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 218 Page - Renesas Technology Corp |
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218 / 919 page ![]() 192 10.1.4 Block Diagrams Overall Block Diagram of ATU-II: Figure 10.1 shows an overall block diagram of the ATU-II. IC/OC control I/O interrupt control Counter and register control, and comparator TCLKA TCLKB Interrupts Inter-module connection signals External pins Inter-module address bus Module data bus Inter-module data bus Legend: TSTR1, 2, 3: Timer start registers (8 bits) Interrupts: ITV0 to ITV2, OVI0, OVI1A, OVI1B, OVI2A, OVI2B, OVI3 to OVI5, OVI11, ICI0A to ICI0D, IMI1A to IMI1H, CMI1, IMI2A to IMI2H, CMI2A to CMI2H, IMI3A to IMI3D, IMI4A to IMI4D, IMI5A to IMI5D, CMI6A to CMI6D, CMI7A to CMI7D, OSI8A to OSI8P, CMI9A to CMI9F, CMI10A, CMI10B, ICI10A, CMI10G, IMI11A, IMI11B External pins: TI0A to TI0D, TIO1A to TIO1H, TIO2A to TIO2H, TIO3A to TIO3D, TIO4A to TIO4D, TIO5A to TIO5D, TO6A to TO6D, TO7A to TO7D, TO8A to TO8P, TI9A to TI9F, TI10 Inter-module connection signals: Signals to A/D converter, signals to direct memory access controller (DMAC), signals to advanced pulse controller (APC) . . . . . . . . Pø Figure 10.1 Overall Block Diagram of ATU-II |
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