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SH7052 Datasheet(PDF) 220 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 220 Page - Renesas Technology Corp |
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220 / 919 page  194 Block Diagram of Channel 1: Figure 10.3 shows a block diagram of ATU-II channel 1. Control logic I/O control Internal data bus and address bus TIO1A TIO1B TIO1C TIO1D TIO1E TIO1F TIO1G TIO1H STR1A/2B Prescaler 1 TCLKA TCLKB TI10 (AGCK) TI10 multiplication (AGCKM) One-shot start trigger (CH8) TRG1A (counter clear trigger from CH10) TRG1B (counter clear trigger from CH10) One-shot terminate trigger (CH8) Overflow interrupt × 1 Input capture/output compare interrupts × 8 GR1A GR1B GR1C GR1D GR1E GR1F GR1G GR1H OSBR1 TCNT1A Clock selection logic (2 systems: A, B) TI0A(capture signal from CH0) Compa- rator OCR1 TCNT1B TIOR1A TIOR1B TIOR1C TIOR1D TCR1A TCR1B TSR1A TSR1B TIER1A TIER1B TRGMDR Figure 10.3 Block Diagram of Channel 1 |
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