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SH7052 Datasheet(PDF) 222 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 222 Page - Renesas Technology Corp |
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222 / 919 page  196 Block Diagram of Channels 3 to 5: Figure 10.5 shows a block diagram of ATU-II channels 3, 4, and 5. Control logic I/O control Internal data bus and address bus TIO3A TIO3B TIO3C TIO3D TIO4A TIO4B TIO4C TIO4D TIO5A TIO5B TIO5C TIO5D STR3 to 5 Prescaler 1 TCLKA TCLKB TI10 (AGCK) TI10 multiplication (AGCKM) Channel 9 compare- match trigger Overflow interrupts × 3 Input capture/output compare interrupts × 12 GR3D TCNT3 TIOR3A TIOR3B TCR3 GR5D TCNT5 TIOR5A TIOR5B TCR5 TMDR TIER3 TSR3 GR3A Clock selection logic (3 systems: CH3, 4, 5) Compa- rator GR4A GR4D TCNT4 TIOR4A TIOR4B TCR4 GR5A • • • • • • • • • Figure 10.5 Block Diagram of Channels 3 to 5 |
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