| Electronic Components Datasheet Search |
|
SH7052 Datasheet(PDF) 219 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
SH7052 Datasheet(HTML) 219 Page - Renesas Technology Corp |
|
219 / 919 page ![]() 193 Block Diagram of Channel 0: Figure 10.2 shows a block diagram of ATU-II channel 0. A/D converter trigger TRGOD (OCR10B compare-match signal) Control logic I/O control OSBR (ch1, ch2) Internal data bus and address bus STR0 TI0A TI0B TI0C TI0D Prescaler 1 Overflow interrupt signal Interval interrupt TIOR0 TIER0 ITVRR1 ITVRR2A ITVRR2B TSR0 ICR0AL ICR0BL ICR0CL ICR0DL TCNT0L ICR0AH ICR0BH ICR0CH ICR0DH TCNT0H Figure 10.2 Block Diagram of Channel 0 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |