SH7052 datasheet(242/919 Pages) RENESAS

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Timer Control Registers 9A, 9B, 9C (TCR9A, TCR9B, TCR9C)

TCR9A

Bit:

43210

—

TRG3BEN EGSELB1 EGSELB0

—

TRG3AEN EGSELA1 EGSELA0

Initial value:

00000

R/W:

R/W

TCR9B

Bit:

43210

—

TRG3DEN EGSELD1 EGSELD0

—

TRG3CEN EGSELC1 EGSELC0

Initial value:

00000

R/W:

R/W

TCR9C

Bit:

43210

——

EGSELF1 EGSELF0

——

EGSELE1 EGSELE0

Initial value:

00000

R/W:

R/W

• Bit 7—Reserved: This bit always reads 0. The write value should always be 0.

• Bit 6—Trigger Channel 3BEN, 3DEN (TRG3BEN, TRG3DEN): These bits select the channel

9 event counter compare-match signal channel 3 input capture trigger.

Bit 6: TRG3xEN

Description

Channel 3 input capture trigger in event of channel 9 compare-match

(ECNT9x = GR9x) is disabled

(Initial value)

Channel 3 input capture trigger in event of channel 9 compare-match

(ECNT9x = GR9x) is enabled

x = B or D

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