SH7243 datasheet(389/1726 Pages) RENESAS

389 / 1726 page

Section 9 Bus State Controller (BSC)

Rev. 1.00 Jun. 26, 2008 Page 359 of 1692

REJ09B0393-0100

9.5.7

Burst ROM (Clock Asynchronous) Interface

The burst ROM (clock asynchronous) interface is used to access a memory with a high-speed read

function using a method of address switching called burst mode or page mode. In a burst ROM

(clock asynchronous) interface, basically the same access as the normal space is performed, but

the 2nd and subsequent access cycles are performed only by changing the address, without

negating the

RD signal at the end of the 1st cycle. In the 2nd and subsequent access cycles,

addresses are changed at the falling edge of the CK.

For the 1st access cycle, the number of wait cycles specified by the W3 to W0 bits in CSnWCR is

inserted. For the 2nd and subsequent access cycles, the number of wait cycles specified by the W1

to W0 bits in CSnWCR is inserted.

In the access to the burst ROM (clock asynchronous), the

BS signal is asserted only to the first

access cycle. An external wait input is valid only to the first access cycle.

In the single access or write access that does not perform the burst operation in the burst ROM

(clock asynchronous) interface, access timing is same as a normal space.

Table 9.17 lists a relationship between bus width, access size, and the number of bursts. Figure

9.35 shows a timing chart.

SH7243 Datasheet(PDF) 389 Page - Renesas Technology Corp