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SH7243 Datasheet(PDF) 390 Page - Renesas Technology Corp |
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SH7243 Datasheet(HTML) 390 Page - Renesas Technology Corp |
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390 / 1726 page  Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 360 of 1692 REJ09B0393-0100 Table 9.17 Relationship between Bus Width, Access Size, and Number of Bursts Bus Width Access Size CSnWCR. BST[1:0] Bits Number of Bursts Access Count 8 bits 8 bits Not affected 1 1 16 bits Not affected 2 1 32 bits Not affected 4 1 x0 16 1 16 bytes 10 4 4 16 bits 8 bits Not affected 1 1 16 bits Not affected 1 1 32 bits Not affected 2 1 00 8 1 01 2 4 4 2 16 bytes 10* 2, 4, 2 3 Note: * When the bus width is 16 bits, the access size is 16 bits, and the BST[1:0] bits in CSnWCR are 10, the number of bursts and access count depend on the access start address. At address H'xxx0 or H'xxx8, 4-4 burst access is performed. At address H'xxx4 or H'xxxC, 2-4-2 burst access is performed. |
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