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SH7243 Datasheet(PDF) 388 Page - Renesas Technology Corp |
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SH7243 Datasheet(HTML) 388 Page - Renesas Technology Corp |
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388 / 1726 page  Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 358 of 1692 REJ09B0393-0100 • Deep power-down mode The low-power SDRAM supports deep power-down mode as a low-power consumption mode. In the partial self-refresh function, self-refresh is performed on a specific area. In deep power- down mode, self-refresh will not be performed on any memory area. This mode is effective in systems where all of the system memory areas are used as work areas. If the RMODE bit in the SDCR is set to 1 while the DEEP and RFSH bits in the SDCR are set to 1, the low-power SDRAM enters deep power-down mode. If the RMODE bit is cleared to 0, the CKE signal is pulled high to cancel deep power-down mode. Before executing an access after returning from deep power-down mode, the power-up sequence must be re-executed. Tpw Tp Tdpd Trc Hi-Z Trc Trc Trc Trc CK CKE A25 to A0 CSn RD/ WR RASL DQMxx D15 to D0 BS DACKn*2 A12/A11*1 CASL Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.34 Deep Power-Down Mode Transition Timing |
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