SH7243 datasheet(403/1726 Pages) RENESAS

Part #	SH7243

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

PDF	1726 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 9 Bus State Controller (BSC)

Rev. 1.00 Jun. 26, 2008 Page 373 of 1692

REJ09B0393-0100

Table 9.21

Number of Idle Cycles Inserted between Access Cycles to Different Memory

Types

Next Cycle

Previous Cycle SRAM

Burst ROM

(Asynchronous)

MPX-

I/O

Byte SRAM

(BAS = 0)

Byte SRAM

(BAS = 1)

SDRAM

(Low-Frequency

Mode)

Burst ROM

(Synchronous)

SRAM

1.5

Burst ROM

(asynchronous)

1.5

MPX-I/O

1.5

Byte SRAM

(BAS = 0)

1.5

Byte SRAM

(BAS = 1)

1.5

SDRAM



SDRAM

(low-frequency

mode)

1.5

2.5

1.5

0.5



1.5

Burst ROM

(synchronous)

1.5

Figure 9.42 shows sample estimation of idle cycles between access cycles. In the actual operation,

the idle cycles may become shorter than the estimated value due to the write buffer effect or may

become longer due to internal bus idle cycles caused by stalling in the pipeline due to CPU

instruction execution or CPU register conflicts. Please consider these errors when estimating the

idle cycles.

SH7243 Datasheet(PDF) 403 Page - Renesas Technology Corp

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