SH7243 datasheet(414/1726 Pages) RENESAS

414 / 1726 page

Section 10 Direct Memory Access Controller (DMAC)

Rev. 1.00 Jun. 26, 2008 Page 384 of 1692

REJ09B0393-0100

10.3

The DMAC has the registers listed in table 10.2. There are four control registers and three reload

registers for each channel, and one common control register is used by all channels. In addition,

there is one extension resource selector per two channels. Each channel number is expressed in the

Table 10.2

Channel

Abbreviation R/W

Initial Value

Address

Access

Size

DMA source address

register_0

SAR_0

R/W

H'00000000

H'FFFE1000

16, 32

DMA destination

address register_0

DAR_0

R/W

H'00000000

H'FFFE1004

16, 32

DMA transfer count

register_0

DMATCR_0

R/W

H'00000000

H'FFFE1008

16, 32

DMA channel control

register_0

CHCR_0

R/W*

H'00000000

H'FFFE100C

8, 16, 32

DMA reload source

address register_0

RSAR_0

R/W

H'00000000

H'FFFE1100

16, 32

DMA reload destination

address register_0

RDAR_0

R/W

H'00000000

H'FFFE1104

16, 32

DMA reload transfer

count register_0

RDMATCR_0 R/W

H'00000000

H'FFFE1108

16, 32

DMA source address

register_1

SAR_1

R/W

H'00000000

H'FFFE1010

16, 32

DMA destination

address register_1

DAR_1

R/W

H'00000000

H'FFFE1014

16, 32

DMA transfer count

register_1

DMATCR_1

R/W

H'00000000

H'FFFE1018

16, 32

DMA channel control

register_1

CHCR_1

R/W*

H'00000000

H'FFFE101C

8, 16, 32

DMA reload source

address register_1

RSAR_1

R/W

H'00000000

H'FFFE1110

16, 32

DMA reload destination

address register_1

RDAR_1

R/W

H'00000000

H'FFFE1114

16, 32

DMA reload transfer

count register_1

RDMATCR_1 R/W

H'00000000

H'FFFE1118

16, 32

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