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SH7243 Datasheet(PDF) 413 Page - Renesas Technology Corp |
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SH7243 Datasheet(HTML) 413 Page - Renesas Technology Corp |
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413 / 1726 page ![]() Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 383 of 1692 REJ09B0393-0100 10.2 Input/Output Pins The external pins for DMAC are described below. Table 10.1 lists the configuration of the pins that are connected to external bus. DMAC has pins for four channels (CH0 to CH3) for SH7286 and two channels (CH0 and CH1) for SH7243 and SH7285, as the external bus use. Table 10.1 Pin Configuration Channel Name Abbreviation I/O Function DMA transfer request DREQ0 I DMA transfer request input from an external device to channel 0 0 DMA transfer request acknowledge DACK0 O DMA transfer request acknowledge output from channel 0 to an external device DMA transfer request DREQ1 I DMA transfer request input from an external device to channel 1 1 DMA transfer request acknowledge DACK1 O DMA transfer request acknowledge output from channel 1 to an external device DMA transfer request DREQ2 I DMA transfer request input from an external device to channel 2 (only in SH7286) 2 DMA transfer request acknowledge DACK2 O DMA transfer request acknowledge output from channel 2 to an external device (only in SH7286) DMA transfer request DREQ3 I DMA transfer request input from an external device to channel 3 (only in SH7286) 3 DMA transfer request acknowledge DACK3 O DMA transfer request acknowledge output from channel 3 to an external device (only in SH7286) 0 DMA transfer end TEND0 O DMA transfer end output for channel 0 1 DMA transfer end TEND1 O DMA transfer end output for channel 1 |
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