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SH7243 Datasheet(PDF) 409 Page - Renesas Technology Corp

Part # SH7243
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family
PDF  1726 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7243 Datasheet(HTML) 409 Page - Renesas Technology Corp

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Section 9 Bus State Controller (BSC)
Rev. 1.00 Jun. 26, 2008 Page 379 of 1692
REJ09B0393-0100
bus, the I bus, and the peripheral bus are synchronized with the I
φ, Bφ, and Pφ clock, respectively.
Figure 9.44 shows an example of the timing of write access to a peripheral bus when I
φ:Bφ:Pφ =
4:4:1. C bus whose are connected to CPU outputs data in synchronization with I
φ. A data transfer
from C bus to I bus requires a period of 2I
φ + Bφ when Iφ:Bφ = 1:1. The transfer from the I bus to
the peripheral bus, when B
φ:Pφ = 4:1, there are 4 clocks exist between Pφ × 1. Thus maximum the
period of 4
× Bφ is required corresponds to the rising edge of Pφ, which the timing of data output
to the peripheral bus from the I bus. When I
φ: Bφ = 4:2, transfer of data from the I bus to the
peripheral bus takes (3
+ n) × Iφ (4 × Bφ is indicated in figure 9.44). The relation between the
timing of data output to the I bus and the rising edge of P
φ depends on the state of program
execution. In the case shown in the figure, where n = 0 and m = 3, the time required for access is 2
× Iφ + 4 × Bφ + 2 × Pφ.
I
φ
C bus
B
φ
I bus
P
φ
Peripheral bus
(1 + m)
× Bφ
2
× Pφ
(2 + n)
× Iφ
Figure 9.44 Timing of Write Access to On-Chip Peripheral I/O Registers
When I
φ;Bφ:Pφ = 4:4:1
Figure 9.45 shows an example of timing of read access to the peripheral bus when I
φ:Bφ:Pφ =
4:2:1. Transfer from the C bus to the peripheral bus is performed in the same way as for write
access. In the case of reading, however, values output onto the peripheral bus must be transferred
to the CPU. Although transfers from the peripheral bus to the I bus and from the I bus to the C bus
are performed in synchronization with the rising edge of the respective bus clocks, a period of (2
+
l)
× Iφ is actually required because Iφ ≥ Bφ≥ Pφ. In the case shown in the figure 9.45, where n = 1,
m = 1, and l = 1, the time required for access is 3
× Iφ + 2 × Bφ + 2 × Pφ + 3 × Iφ.



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