SH7243 datasheet(408/1726 Pages) RENESAS

408 / 1726 page

Section 9 Bus State Controller (BSC)

Rev. 1.00 Jun. 26, 2008 Page 378 of 1692

REJ09B0393-0100

(3)

On-Chip Peripheral Module Access

To access an on-chip module register, two or more peripheral module clock (P

φ) cycles are

required. Care must be taken in system design.

When the CPU writes data to the internal peripheral registers, the CPU performs the succeeding

instructions without waiting for the completion of writing to registers.

For example, a case is described here in which the system is transferring to software standby mode

for power savings. To make this transition, the SLEEP instruction must be performed after setting

the STBY bit in the STBCR register to 1. However a dummy read of the STBCR register is

required before executing the SLEEP instruction. If a dummy read is omitted, the CPU executes

the SLEEP instruction before the STBY bit is set to 1, thus the system enters sleep mode not

software standby mode. A dummy read of the STBCR register is indispensable to complete

writing to the STBY bit.

To reflect the change by internal peripheral registers while performing the succeeding instructions,

execute a dummy read of registers to which write instruction is given and then perform the

succeeding instructions.

Table 9.22 shows the number of cycles required for access to the on-chip peripheral I/O registers

by the CPU.

Table 9.22

Number of Cycles for Access to On-Chip Peripheral module registers

Number of Access Cycles

Write

(2 + n)

× Iφ + (1 + m) × Bφ + 2 × Pφ

Read

(2 + n)

× Iφ + (1 + m) × Bφ + 2 × Pφ + (2 + I) × Iφ

Notes: The above indicates the number of access cycles of which executed when the instructions

are by on-chip ROM or by on-chip RAM.

When I

φ:Bφ = 1:1, n = 0 and I = 0.

When I

φ:Bφ = 2:1, n = 1 to 0 and I = 1.

When I

φ:Bφ = 4:1, n = 3 to 0 and I = 2.

When I

φ:Bφ = 8:1, n = 7 to 0 and I = 2.

When B

φ:Pφ = 1:1, m = 0.

When B

φ:Pφ = 2:1, m = 1 to 0.

When B

φ:Pφ = 4:1, m = 3 to 0.

n and m depend on the internal execution state.

Synchronous logic and a layered bus structure have been adopted for this LSI. Data on each bus

are input and output in synchronization with rising edges of the corresponding clock signal. The C

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