SH7243 datasheet(412/1726 Pages) RENESAS

412 / 1726 page

Section 10 Direct Memory Access Controller (DMAC)

Rev. 1.00 Jun. 26, 2008 Page 382 of 1692

REJ09B0393-0100

• Transfer request acknowledge and transfer end signals: Active levels for DACK and TEND

can be set independently.

• Support of reload functions in DMA transfer information registers: DMA transfer using the

same information as the current transfer can be repeated automatically without specifying the

information again. Modifying the reload registers during DMA transfer enables next DMA

transfer to be done using different transfer information. The reload function can be enabled or

disabled independently in each channel.

Figure 10.1 shows the block diagram of the DMAC.

On-chip

peripheral module

DMA transfer request signal

DMA transfer acknowledge signal

External ROM

On-chip

memory

Interrupt controller

DREQ0 to DREQ3*

HEIn

DACK0 to DACK3,

TEND0, TEND1

External RAM

Bus

interface

Bus state

controller

External device

(memory mapped)

External device

(with acknowledge)

Request

priority

control

Start-up

control

Iteration

control

RDMATCR_n

DMATCR_n

RSAR_n

SAR_n

DAR_n

RDAR_n

CHCR_n

DMAOR

DMARS0

to DMARS3

RDMATCR:

DMATCR:

RSAR:

SAR:

RDAR:

DAR:

DMA reload transfer count register

DMA transfer count register

DMA reload source address register

DMA source address register

DMA reload destination address register

DMA destination address register

CHCR:

DMAOR:

DMARS0 to DMARS3:

HEIn:

DEIn:

n = 0 to 7

DMA channel control register

DMA operation register

DMA extension resource selectors 0 to 3

DMA transfer half-end interrupt request to the CPU

DMA transfer end interrupt request to the CPU

DEIn

[Legend]

Notes: * DREQ0 and DREQ1 (SH7285 and SH7243)

DREQ0 to DREQ3 (SH7286)

DMAC module

Figure 10.1 Block Diagram of DMAC

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