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SH7243 Datasheet(PDF) 458 Page - Renesas Technology Corp |
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SH7243 Datasheet(HTML) 458 Page - Renesas Technology Corp |
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458 / 1726 page  Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 428 of 1692 REJ09B0393-0100 CK DREQ (Rising) DACK (Active-high) Bus cycle Burst acceptance Non sensitive period CPU CPU DMAC DMAC Figure 10.15 Example of DREQ Input Detection in Burst Mode Edge Detection CK DREQ (Overrun 0 at high level) DACK (Active-high) Bus cycle 2nd acceptance CPU CPU DMAC CK DREQ (Overrun 1 at high level) DACK (Active-high) Bus cycle 1st acceptance 2nd acceptance Non sensitive period Non sensitive period CPU CPU DMAC 3rd acceptance DMAC Acceptance start Acceptance start Acceptance start 1st acceptance Figure 10.16 Example of DREQ Input Detection in Burst Mode Level Detection |
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