SH7243 datasheet(459/1726 Pages) RENESAS

459 / 1726 page

Section 10 Direct Memory Access Controller (DMAC)

Rev. 1.00 Jun. 26, 2008 Page 429 of 1692

REJ09B0393-0100

Figure 10.17 shows the TEND output timing.

DACK

DREQ

TEND

Bus cycle

End of DMA transfer

DMAC

CPU

DMAC

Figure 10.17 Example of DMA Transfer End Signal Timing

(Cycle Steal Mode Level Detection)

The unit of the DMA transfer is divided into multiple bus cycles when 16-byte transfer is

performed for an 8-bit or 16-bit external device, when longword access is performed for an 8-bit

or 16-bit external device, or when word access is performed for an 8-bit external device. When a

setting is made so that the DMA transfer size is divided into multiple bus cycles and the

CS signal

is negated between bus cycles, note that DACK and TEND are divided like the

CS signal for data

alignment. Also, if the DREQ detection is set to level-detection mode (DS bit in CHCR = 0), the

DREQ sampling may not be detected correctly with divided DACK, and one extra overrun may

occur at maximum.

Use a setting that does not divide DACK or specify a transfer size smaller than the external device

bus width if DACK is divided. Figure 10.18 shows this example.

SH7243 Datasheet(PDF) 459 Page - Renesas Technology Corp