SH7243 datasheet(103/1726 Pages) RENESAS

103 / 1726 page

Section 4 Clock Pulse Generator (CPG)

Rev. 1.00 Jun. 26, 2008 Page 73 of 1692

REJ09B0393-0100

Section 4 Clock Pulse Generator (CPG)

This LSI has a clock pulse generator (CPG) that generates an internal clock (I

φ), a peripheral

clock (P

φ), a bus clock (Bφ), an MTU2S clock (Mφ), and an AD clock (Aφ). The CPG consists of

a crystal oscillator, a PLL circuit, and a divider circuit.

4.1

Features

• Five clocks generated independently

An internal clock (I

φ) for the CPU and cache, a peripheral clock (Pφ) for the peripheral

modules, a bus clock (B

φ = CK) for the external bus interface, an MTU2S clock (Mφ) for the

MTU2S module, and an AD clock (A

φ) for the ADC module can be generated independently.

• Frequency change function

Internal and peripheral clock frequencies can be changed independently using the PLL (phase

locked loop) circuit and divider circuit within the CPG. Frequencies are changed by software

using frequency control register (FRQCR) settings.

• Power-down mode control

The clock can be stopped for sleep mode and software standby mode, and specific modules

can be stopped using the module standby function. For details on clock control in the power-

down modes, see section 28, Power-Down Modes.

Figure 4.1 shows a block diagram of the clock pulse generator.

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