SH7243 datasheet(104/1726 Pages) RENESAS

104 / 1726 page

Section 4 Clock Pulse Generator (CPG)

Rev. 1.00 Jun. 26, 2008 Page 74 of 1692

REJ09B0393-0100

FRQCR:

MCLKCR:

ACLKCR:

STBCR:

STBCR2:

[Legend]

Frequency control register

MTU2S clock frequency control register

AD clock frequency control register

Standby control register

Standby control register 2

STBCR3:

STBCR4:

STBCR5:

STBCR6:

OSCCR:

Standby control register 3

Standby control register 4

Standby control register 5

Standby control register 6

Oscillation stop detection control register

FRQCR

MCLKCR

ACLKCR

Bus interface

CPG control unit

Clock frequency

control circuit

Standby control circuit

EXTAL

XTAL

PLL circuit

(

×8)

Divider

MTU2S clock

φ, Max. 100 MHz)

AD clock

φ, Max. 50 MHz)

Internal clock

φ, Max. 100 MHz)

Peripheral clock

φ, Max. 50 MHz)

Bus clock

φ = CK, Max. 50 MHz)

OSCCR

Crystal

oscillator

Oscillation

stop detection

circuit

Oscillation stop

detection

On-chip oscillator

HPB bus

STBCR

STBCR6

STBCR2

STBCR3

STBCR4

STBCR5

×1

×1/2

×1/4

×1/8

Oscillator

USBXTAL*

USBEXTAL*

USB clock

φ :48MHz)

Note: * Not applied to the SH7243

Figure 4.1 Block Diagram of Clock Pulse Generator

SH7243 Datasheet(PDF) 104 Page - Renesas Technology Corp

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