SH7243 datasheet(110/1726 Pages) RENESAS

110 / 1726 page

Section 4 Clock Pulse Generator (CPG)

Rev. 1.00 Jun. 26, 2008 Page 80 of 1692

REJ09B0393-0100

FRQCR/MCLKCR/ACLKCR

Division Ratio Setting

Clock Ratio

Clock Frequency (MHz)*

PLL

Multipli-

cation

Ratio

Input Clock

1/1

1/2

1/4

100

1/1

1/2

1/4

1/2

1/4

100

1/1

1/2

1/4

1/2

100

1/1

1/2

1/4

1/1

1/4

100

1/1

1/2

1/4

1/1

1/2

100

1/1

1/2

100

×8

1/1

1/2

1/1

1/2

12.5

100

Notes:

* Clock frequencies when the input clock frequency is assumed to be the shown value.

The PLL multiplication ratio is fixed at ×8. The division ratio can be selected from ×1, ×1/2, ×1/4,

and ×1/8 for each clock by the setting in the frequency control register.

The output frequency of the PLL circuit is obtained by multiplication of the frequency of the input

from the crystal resonator or EXTAL pin and the multiplication ratio (×8) of the PLL circuit. This

output frequency must be 100 MHz or lower.

The input to the divider is always the output from the PLL circuit.

The internal clock (I

φ) frequency is obtained by multiplication of the frequency of the input from the

crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the division ratio

of the divider. The resultant frequency of the internal clock (I

φ) must not exceed 100 MHz

(maximum operating frequency) or lower.

5. The bus clock (B

φ) frequency is obtained by multiplication of the frequency of the input from the

crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the division ratio

of the divider. The resultant frequency of the bus clock (B

φ) must not exceed 50 MHz or the

internal clock (I

φ) frequency.

The peripheral clock (P

φ) frequency is obtained by multiplication of the frequency of the input from

the crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the division

ratio of the divider. The resultant frequency of the peripheral clock (P

φ) must not exceed 50 MHz or

the bus clock (B

φ) frequency.

When using the MTU2S, the MTU2S clock (M

φ) frequency must not exceed the internal clock (Iφ)

frequency. The MTU2S clock (M

φ) frequency is obtained by multiplication of the frequency of the

input from the crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and

the division ratio of the divider.

The frequency of the CK pin output is always equal to the bus clock (B

φ) frequency.

When using the AD, the AD clock (A

φ) frequency must be equal to or higher than the peripheral

clock (P

φ) frequency.

10. When using the USB, the peripheral clock (P

φ) frequency must be 13 MHz or higher.

11. U

φ must be fixed to 48 MHz. When generating Uφ from the divider, input the clock 12 MHz or

connect the crystal resonator of 12MHz to the EXTAL or XTAL.

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