SH7243 datasheet(111/1726 Pages) RENESAS

111 / 1726 page

Section 4 Clock Pulse Generator (CPG)

Rev. 1.00 Jun. 26, 2008 Page 81 of 1692

REJ09B0393-0100

4.4

The clock pulse generator has the following registers.

Table 4.4

Abbreviation R/W

Initial Value Address

Access Size

Frequency control register

FRQCR

R/W

H'0333

H'FFFE0010 16

MTU2S clock frequency

control register

MCLKCR

R/W

H'43

H'FFFE0410 8

AD clock frequency control

ACLKCR

R/W

H'43

H'FFFE0414 8

Oscillation stop detection

control register

OSCCR

R/W

H'00

H'FFFE001C 8

4.4.1

Frequency Control Register (FRQCR)

FRQCR is a 16-bit readable/writable register used to specify whether a clock is output from the

CK pin in software standby mode, the frequency multiplication ratio of PLL circuit 1, and the

frequency division ratio of the internal clock (I

φ) and peripheral clock (Pφ). FRQCR can be

accessed only in word units. After executing an instruction for modifying the FRQCR, be sure to

execute 32 NOP instructions. Especially when writing/erasing to the flush memory, execute the

NOP operation for 32P

φ clock after having confirmed the set value by reading the FRQCR.

FRQCR is initialized to H'0333 only by a power-on reset. FRQCR retains its previous value by a

manual reset or in software standby mode. The previous value is also retained when an internal

reset is triggered by an overflow of the WDT.

When switching the division ratio of bus clock frequency, the CK pin is fixed at low level for a

cycle of an input clock so as to prevent a hazard of switching.

9876543210

Bit:

Initial value:

R/W:

000

00110011

011

RRR

R/W

---

IFC[2:0]

STC[2:0]

PFC[2:0]

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