SH7243 datasheet(115/1726 Pages) RENESAS

115 / 1726 page

Section 4 Clock Pulse Generator (CPG)

Rev. 1.00 Jun. 26, 2008 Page 85 of 1692

REJ09B0393-0100

4.4.3

AD Clock Frequency Control Register (ACLKCR)

ACLKCR is an 8-bit readable/writable register that can be accessed only in byte units. ACLKCR

is initialized to H'43 only by a power-on reset, but retains its previous value by a manual reset or

in software standby mode.

7654321

01000011

R/W

Bit:

Initial value:

R/W:

ASSCS[1:0]

ASDIVS[1:0]

----

Bit

Bit Name

Initial

Value

R/W

Description

7, 6

ASSCS[1:0]

R/W

Source Clock Select

These bits select the source clock.

00: Clock stoppage

01: PLL output clock

10: Reserved (setting prohibited)

11: Reserved (setting prohibited)

5 to 2



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

1, 0

ASDIVS[1:0] 11

R/W

Division Ratio Select

These bits specify the frequency division ratio of the

source clock. Set these bits so that the output clock is

50 MHz or less, and also an integer multiple of the

peripheral clock frequency (P

φ).

00:

× 1

01:

× 1/2

10: Setting prohibited

11:

× 1/4

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