SH7243 datasheet(117/1726 Pages) RENESAS

117 / 1726 page

Section 4 Clock Pulse Generator (CPG)

Rev. 1.00 Jun. 26, 2008 Page 87 of 1692

REJ09B0393-0100

4.5

Changing the Frequency

Selecting division ratios for the frequency divider can change the frequencies of the internal clock,

bus clock, peripheral clock, and MTU2 clock under the software control through the frequency

control register (FRQCR). The following describes how to specify the frequencies.

1. In the initial state, IFC2 to IFC0 = B'011 (

×1/4), STC2 to STC0 = B'011 (×1/4), PFC2 to PFC0

= B'011 (

×1/4), MSDIVS1 and MSDIVS0 = 11 (×1/4), and ASDIVS1 and ASDIVS 0 = 11

(

×1/4).

2. Stop all modules except the CPU, on-chip ROM, and on-chip RAM.

3. Set the desired values in bits IFC2 to IFC0, STC2 to STC0, PFC2 to PFC0, MSDIVS1,

MSDIVS0, ASDIVS1, and ASDIVS 0. When specifying the frequencies, satisfy the following

condition: internal clock (I

φ) ≥ bus clock (Bφ) ≥ peripheral clock (Pφ). When using the

MTU2S clock, specify the frequencies to satisfy the following condition: internal clock (I

φ) ≥

MTU2S clock (MI

φ) ≥ peripheral clock (Pφ).

4. The clock frequencies are immediately changed to the specified values after FRQCR setting is

completed.

SH7243 Datasheet(PDF) 117 Page - Renesas Technology Corp