SH7243 datasheet(120/1726 Pages) RENESAS

120 / 1726 page

Section 4 Clock Pulse Generator (CPG)

Rev. 1.00 Jun. 26, 2008 Page 90 of 1692

REJ09B0393-0100

4.7

Oscillation Stop Detection

The CPG detects a stop in the clock input if any system abnormality halts the clock supply.

When no change has been detected in the EXTAL input for a certain period, the OSCSTOP bit in

OSCCR is set to 1 and this state is retained until a power-on reset is input through the

RES pin is

canceled. If the OSCERS bit is 1 at this time, an oscillation stop detection flag signal is output

through the

WDTOVF pin. In addition, the high-current ports (multiplexed pins to which the

TIOC3B, TIOC3D, and TIOC4A to TIOC4D signals in the MTU2, the TIOC3BS, TIOC3DS, and

TIOC4AS to TIOC4DS in the MTU2S are assigned) can be placed in high-impedance state

regardless of the PFC setting. For details, refer to appendix A, Pin States.

Even in software standby mode, these pins are placed in high-impedance state. For details, refer to

appendix A, Pin States. Under an abnormal condition where oscillation stops while the LSI is not

in software standby mode, LSI operations other than the oscillation stop detection function

become unpredictable. In this case, even after oscillation is restarted, LSI operations including the

above high-current pins become unpredictable.

Even while no change is detected in the EXTAL input, the PLL circuit in this LSI continues

oscillating at a frequency range from 100 kHz to 10 MHz (depending on the temperature and

operating voltage).

SH7243 Datasheet(PDF) 120 Page - Renesas Technology Corp