SH7243 datasheet(124/1726 Pages) RENESAS

124 / 1726 page

Section 4 Clock Pulse Generator (CPG)

Rev. 1.00 Jun. 26, 2008 Page 94 of 1692

REJ09B0393-0100

4.9

Notes on Board Design

4.9.1

Note on Using an External Crystal Resonator

Place the crystal resonator and capacitors CL1 and CL2 as close to the XTAL and EXTAL pins as

possible. In addition, to minimize induction and thus obtain oscillation at the correct frequency,

the capacitors to be attached to the resonator must be grounded to the same ground. Do not bring

wiring patterns close to these components.

CL1

CL2

EXTAL

XTAL

Signal lines prohibited

This LSI

The values for CL1 and CL2

should be determined after

consultation with the crystal

resonator manufacturer.

Note:

Reference value

CL1 = 20 pF

CL2 = 20 pF

Figure 4.9 Note on Using a Crystal Resonator

A circuitry shown in figure 4.10 is recommended as an external circuitry around the PLL. PLLVss

must be separated from Vcc and Vss at the board power supply source. Be sure to insert bypass

capacitors CB and CPB close to the Vcc and Vss pins.

PLLV

CPB = 0.1

µF*

CB = 0.1

µF*

Note: * CB and CPB are laminated ceramic capacitors.

(Recommended values are shown.)

Figure 4.10 Recommended External Circuitry around PLL

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